1. Field of the Invention
The present invention relates generally to methods of manufacturing and devices for interconnects in integrated semiconductor circuits. More particularly, the invention relates to methods of fabricating and devices for electromagnetic shielded interconnects. These devices are implemented in a damascene process flow.
2. Description of the Related Art
The increasing operation frequency of state-of-the-art VLSI circuits is nowadays mainly limited by the speed at which electromagnetic (EM) signals can be conveyed from one high speed building block to another building block on the semiconductor chip. These high frequency signals are being transmitted through an interconnect scheme comprising multiple levels of, typically metallic, conductors spaced apart and electrically isolated in lateral and vertical direction by layers of dielectric materials. These interconnect planes or levels can be interconnected in vertical direction by xe2x80x9cviasxe2x80x9d or openings formed in the surrounding dielectrics and filled with a conductive material.
In semiconductor process technology fundamental two interconnect fabrication options exist: substructive etch of metal or the damascene approach. In the first process option each interconnect level is formed by first depositing metal on top of a dielectric layer belonging to a lower interconnect level, then patterning metal lines and covering this metal pattern with a layer of dielectric, the so-called inter-metal dielectric (IMD). In this IMD layer openings, i.e. contact or xe2x80x9cviaxe2x80x9d, to the underlying metal pattern are defined and finally these openings in the dielectric layer are filled with a metal. In the last process option each interconnect level is formed by first depositing and planarizing the dielectric material (IMD) followed by the etching of openings in this dielectric stack. These openings and serve as molds for the via and trench pattern. Finally the openings, grooves or indents are filled with metal. In the single damascene process the damascene process sequence is repeated to pattern and metallize respectively the opening and trench, while in the dual damascene process both opening and trench are patterned and metallized together. The damascene option is the preferred back-end-of-line process sequence for manufacturing advanced semiconductor chips. A comparison between these two interconnect architectures is given in xe2x80x9cOverview of process integration issues for low-k dielectricsxe2x80x9d by R. Havermann et al. in the 1998 proceedings of the Material Research Society vol 511, hereby incorporated by reference in its entirety.
As the conductors, characterized by a given resistivity p, are embedded in dielectric materials, characterized by a given dielectric constant k, the electromagnetic signals guided by these conductors will suffer from the distributed capacitive load introduced by these surrounding dielectrics. This capacitive load together with the resistance of the conductor adds a RC delay to the signal propagation and increases the response time of the interconnect scheme. More problematic, signals transmitted through neighboring conductors, lying in the same or in adjacent interconnect planes, will be electromagnetically coupled. Hence electromagnetic interference, such as cross-talk and ringing, between adjacent signal lines occurs. Examples of signals that are particularly sensitive to these electromagnetic interference problems are the clock signals, governing the synchronization of the various functional blocks of a circuit. Furthermore, these clock signals require a signal distribution scheme from the clock input down to the individual components at lower levels on the wafer. Consequently the signal path the clock signals have to follow is quite long, thus more subject to the effects of propagation delay and electromagnetic interference.
In xe2x80x9cEmbedded ground planes using sidewall insulators for high frequency interconnections in integrated circuitsxe2x80x9d by D. Gardner et al. presented at the IEDM conference of 1993, pp. 251-254, an interconnect structure is disclosed containing a ground plane. This ground plane is an intermediate metal plane located in between two superposed interconnect levels. The proposed interconnect scheme offers a ground plane as is the case for example in microstrip lines. This ground plane is also capable of electromagnetic shielding the interconnect levels above this ground plane from the interconnect levels below, if the ground plane is present substantially all over the chip. However no shielding of signal lines within the same interconnect level is obtained, although these signal lines are more prone to electromagnetic interference. The proposed interconnect scheme requires an additional metal level and doesn""t offer the flexibility of only shielding selected signal lines.
Another approach is outlined in xe2x80x9cVLSI multilevel micro-coaxial interconnects for high speed devicesxe2x80x9d by M. Thomas et al. presented at the IEDM conference of 1990, pp. 55-58. The author proposes to form a coax-like structure by first forming an interconnect level and afterwards removing the dielectric material underneath the conductors and in between the openings. The chip surface is then uniformly covered with a stack of a conformal CVD dielectric and a conformal metal layer forming a contiguous metal shield encapsulating the freestanding metal structure. The proposed interconnect structure will shield the encapsulated conductor from the higher interconnect levels and from the signal lines at the same interconnect level. The corresponding process sequence is however quite complex relying e.g. on a selective etch-back of the dielectric, the mechanical stability of the freestanding conductor, tight conformal deposition of the dielectric and metal layer forming respectively the intermediate dielectric and the shield of this coax-like structure. The proposed interconnect scheme doesn""t offer the flexibility of only shielding selected signal lines and can not be used to shield dense patterns or tighter spaced signal lines or interconnect patterns.
In the international application WO 0131706 to S. Bothra et al., a method of fabricating coaxial RF lines for CMOS circuits is disclosed. The interconnects are formed by substructive etch of metal and dielectric. The proposed sequence is very complex and consists of first forming the bottom part of the shield and the insulator, then forming the metal core and the top part of the shield and the insulator by etching a stack of metal and dielectric layers and finally forming the side-parts of the insulator and the shield. This process sequence allows the formation of an RF line and a CMOS line within the same metal layer but at the expense of adding a multitude of additional patterning steps, i.e. lithographic and etch steps. This additional processing requires correct alignment of subsequent patterned elements. Line spacing between RF lines must be increased to allow the formation of the side parts of the shield and insulator.
An aim of the present invention is to provide a coaxial interconnect scheme implemented in a damascene process technology.
An aim of the present invention is to provide shielded or coaxial interconnects for integrated circuits, preferably CMOS integrated circuits, by using a process technology based on a single or dual damascene technology.
An aim of the present invention is to provide a coaxial interconnect whereby at least the bottom and the sideparts of the shield and the insulator are formed simultaneously and self-aligned to the core of the coaxial interconnect.
An aim of the present invention is to provide an interconnect scheme implemented in a damascene back-end-of-line technology to shield selected interconnect lines.
An aim of the present invention is to provide an interconnect scheme comprising a common ground plane implemented in a damascene back-end-of-line technology.
An aim of the present invention is to provide shielded interconnects for integrated circuits by using a process technology based on a single or dual damascene technology, whereby said shielding of an interconnect level or line is realized at the stage of forming the interconnect level or interconnect line.
An aim of the present invention is to combine RF devices or circuits with a CMOS circuitry on a single, preferably semiconductor, substrate by means of a damascene based shielded wiring.
In a first embodiment a shielded damascene interconnect line is presented comprising at least two independent formed conductors isolated one from another. One conductor acts as a core conductor of a coaxial interconnect, while a shield conductor that wraps the bottom and the two sides of the core conductor. Process steps are outlined to implement the additional processing in the standard damascene technology. The basic technology suitable for this type of interconnects is the known damascene technology. After patterning the vias a first metal layer is created. Subsequently an intermediate dielectric e.g. SiC is formed, e.g. deposited by CVD, ALCVD or other ways known to a person skilled in the art, followed by forming the core metal. In accordance with the Cu damascene technology, the barrier layer of this technology can be used as the shield conductor and the intermediate dielectric between the two conductors, the insulator, can be any low-k material or any other suitable dielectric material. The Cu deposited on the insulator layer becomes the core layer of the coaxial interconnect. This Cu is used to fill the trenches and/or vias depending on the interconnect scheme. The shield and the insulator need to be optimized for thickness and are both preferably very thin. Alternatively a third conductor, a so-called guard, is added by using processing steps and methods similar to these applied in other embodiments.
In a second embodiment of the present invention materials other than the standard damascene materials are used to form the shield and the intermediate dielectric.